Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, Flash, etc. A MRAM device is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and an MTJ element interposed between a first conductive line and a second conductive line at each crossover location. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Alternatively, a first conductive line may be a bottom electrode that is a sectioned line while a second conductive line is a bit line (or word line). There are typically other devices including transistors and diodes below the array of first conductive lines as well as peripheral circuits used to select certain MRAM cells within the MRAM array for read or write operations.
An MTJ element may be based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. An MTJ stack of layers may be formed in a so-called bottom spin valve configuration by sequentially depositing a seed layer, an anti-ferromagnetic (AFM) pinning layer, a ferromagnetic “pinned” layer, a thin tunnel barrier layer, a ferromagnetic “free” layer, and a capping layer on a substrate.
The AFM layer holds the magnetic moment of the pinned layer in a fixed direction. The pinned layer has a magnetic moment that is fixed in the “y” direction, for example, by exchange coupling with the adjacent AFM layer. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer and is preferably made of NiFe because of its reproducible and reliable switching characteristics as demonstrated by a low switching field (Hc) and switching field uniformity (σHc). The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
In a read operation, the information stored in a MRAM cell is read by sensing the magnetic state (resistance level) of the MTJ element through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the MRAM cell by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. In certain MRAM architectures, the top electrode or the bottom electrode participates in both read and write operations.
Generally, the purpose of the capping layer is to protect underlying layers in the MTJ during etching and other process steps and to function as an electrical contact to an overlying conductive line. In the fabrication of MRAM devices, ion beam etching (IBE) is often used to create MTJ cell arrays. However, IBE typically produces sloped sidewalls on the MTJ cell such that the top surface (capping layer) has a smaller width than the bottom surface (seed layer). A sloped profile can not only lead to electrical shorting issues but also limits further reduction of linewidth and makes it impossible to manufacture a very high density IC device as is required for applications such as spin torque MRAM. Spin transfer (spin torque) magnetization switching is described by J. Sloneczewski in “Current-driven excitation of magnetic multilayers”, J. Magn. Materials V 159, L1-L7 (1996), and by L. Berger in “Emission of spin waves by a magnetic multiplayer traversed by a current” in Phys. Rev. Lett. B, Vol. 52, p 9353. The difference between a Spin-RAM and a conventional MRAM is only in the write operation mechanism. The read mechanism is the same.
A better approach to create a well defined three dimensional micro feature is by reactive ion etch (RIE) where a chemical reaction enables easy removal of by-products formed through the interaction of gaseous reactants and the materials to be removed. In the current MRAM fabrication process, a heavy metal such as Ta is deposited on top of a MTJ stack of layers, and acts both as a hard mask for the etching of the MTJ stack and also as an interlayer conduction channel to the top bit line as described in U.S. Pat. No. 7,060,194 which is represented by the process flow in FIGS. 1a-1d. Referring to FIG. 1a, a partially formed MRAM cell 1 is shown in which a photoresist layer 7 is patterned above a Ta hard mask 6 and a MTJ stack of layers 3-5 formed on a bottom electrode 2. In FIG. 1b, the photoresist pattern is transferred through the Ta hard mask to form a hard mask feature 6a followed by removal of the photoresist layer. In FIG. 1c, the hard mask feature 6a serves as an etch mask for transferring the hard mask pattern through the underlying MTJ stack to form a MTJ cell made of layers 3a-6a. There is a certain amount of Ta thickness loss in the hard mask feature 6a that may also be considered as a capping layer in the MTJ cell. In FIG. 1d, a first insulation layer 8 is shown between adjacent bottom electrodes 2 and a second insulation layer 9 is deposited adjacent to the MTJ cell comprised of layers 3a-6a, and planarized with some further Ta thickness loss in the hard mask layer 6a before a bit line 10 is added in a subsequent step. In some cases, the thickness of hard mask layer 6a (FIG. 1d) may be too small and electrical shorting occurs between the bit line 10 and the lower layer 3a of the MTJ cell. For example, MTJ layer 3a may represent a composite comprising a seed layer, AFM layer, and pinned layer while MTJ layer 4a is a tunnel barrier, MTJ layer 5a is a free layer, and hard mask layer 6a may function as a capping layer.
For sub-micrometer sized MTJ cells, a single Ta hard mask may not be a problem. However, as the MTJ cell/pitch dimensions shrink to about 100 nm or less as required for spin torque MRAMs, the MTJ shapes generated by a RIE process may not be able to withstand subsequent CMP processing and bit line via (BLV) etching and often result in device failure due to electrical shorting between the lower portion of the MTJ cell and bit line. In the example depicted in FIG. 2a, the top surface of capping layer 53 in a conventional MTJ cell is seen from a top view and has a typical elliptical shape after a patterning and etching sequence is used to form an opening for a subsequently deposited bit line in a second insulation layer 58 above the capping layer 53. The capping layer 53 and underlying portions of the MTJ cell (not shown) are surrounded by a first insulation layer 54 that is coplanar with the capping layer except for a region adjacent to the capping layer 53 which is a depression 56. The depression 56 is formed in the first insulation layer 54 because of the preceding RIE step that etches the dielectric material in the first insulation layer 54 at a faster rate than the capping layer 53. In order to clear dielectric material from the top surface of the capping layer 53, the surrounding region of first insulation layer 54 is overetched. From a cross-sectional view in FIG. 2b taken from the plane 59-59 in FIG. 2a, sidewalls 57 along the MTJ cell are partially uncovered by the preceding RIE etch. The upper layer 53 may be a composite made of a lower free layer and upper capping layer while the middle layer 52 is a tunnel barrier and the lower layer 51 may be a composite having a seed layer/AFM/pinned layer configuration formed on a bottom electrode 50. FIG. 2c shows that after a bit line 55 is deposited to fill an opening in a second insulation layer formed on the first insulation layer, the metal in bit line 55 also fills the depression adjacent to the sidewalls 57 (FIG. 2b) and makes contact with a portion of the lower layer 51 below the tunnel barrier and thereby causes an electrical short in the device.
Fabrication of MTJ cell dimensions of about 100 nm or less requires a thin photoresist layer (<3000 Angstroms) to ensure an adequate process latitude when imaging small MTJ features on a hard mask that will later be transferred through the hard mask and a MTJ stack of layers. It is well known that an aspect ratio (thickness/width of a pattern feature) of about 3:1 or less is preferred to avoid pattern collapse during image development. However, a thin photoresist layer requires a thin Ta hard mask layer to guarantee that the hard mask pattern will be completely formed before the photoresist etch mask is consumed during the etch transfer step. Unfortunately, a thin Ta hard mask leads to potential issues of electrical shorting as mentioned previously and limits the amount of etch time available to transfer the hard mask pattern through the MTJ stack of layers because the hard mask erodes during the pattern transfer process. Thus, other alternatives besides a simple Ta hard mask are necessary when fabricating MTJ cells having an easy axis or hard axis dimension of about 100 nm or less.
One alternative described in U.S. Pat. No. 7,001,783 is a bilayer hard mask consisting of an upper dielectric layer made of SiO2, silicon nitride, silicon carbide, or the like, and a lower heavy metal layer (Ta) that contacts the free layer in the MTJ stack of layers. The MTJ fabrication sequence is represented in FIGS. 3a-3d. In FIG. 3a, a partially formed MRAM 11 is depicted in which a photoresist layer 18 is patterned above a bilayer made of an upper dielectric layer 17 and a lower metal layer 16. The bilayer is formed on a MTJ stack of layers consisting of a lower first magnetic layer 13, a middle tunnel barrier 14, and an upper second magnetic layer 15. In FIG. 3b, the photoresist pattern is transferred through the dielectric layer to form a dielectric layer pattern 17a. After the photoresist is removed, a second etch step (FIG. 3c) transfers the dielectric layer pattern through the lower metal layer to form a metal pattern 16a. Thereafter, in FIG. 3d, the pattern is transferred through the MTJ stack of layers to form a MTJ cell comprised of etched layers 13a-15a on a bottom electrode 12. In this process flow, the dielectric layer 17 acts as a sacrificial layer to prevent excessive etching of the Ta hard mask 16 during the final etch of the MTJ stack of layers. However, this approach usually employs chlorine based chemicals to achieve a high etch selectivity between the bilayer materials SiO2 and Ta. Chlorine based chemicals can lead to device corrosion. Furthermore, the requirement for a sufficiently thick hard mask between the bit line and MTJ free layer is not met because the dielectric layer 17 is sacrificed and electrical shorting is still a possibility because of the thin lower metal layer 16. Therefore, a new MTJ hard mask design is needed to allow a thicker hard mask layer to avoid electrical shorting without compromising the photolithography process latitude required when printing sub-100 nm features.
Additional references were found during a routine search of the prior art. In U.S. Pat. No. 6,984,529, a patterned hard mask is oxidized to form an oxide surface before etching the underlying MTJ stack of layers to form a MTJ element.
In U.S. Pat. No. 7,252,774, a passivation layer such as Ta or TaN is patterned on a MTJ stack of layers followed by wet etching or RIE etching to remove at least the upper layer in the MTJ stack.